 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| final publication# 18723 rev: c amendment/ +1 issue date: may 1998 amc0xxcflka 1, 2, 4, or 10 megabyte 5.0 v-only flash memory pc card distinctive characteristics n high performance 150 ns maximum access time n single supply operation write and erase voltage, 5.0 v 5% read voltage, 5.0 v 5% n cmos low power consumption 45 ma maximum active read current (x8 mode) 65 ma maximum active erase/write current (x8 mode) n high write endurance minimum 100,000 erase/write cycles n pcmcia/jeida 68-pin standard selectable byte- or word-wide configuration n write protect switch prevents accidental data loss n zero data retention power batteries not required for data storage n separate attribute memory 512 byte eeprom n automated write and erase operations increase system write performance 64k byte memory sectors for faster automated erase speed typically 1.5 seconds per single memory sector erase random address writes to previously erased bytes (16 s typical per byte) n total system integration solution support from independent software and hardware vendors n low insertion and removal force state-of-the-art connector allows for minimum card insertion and removal effort n sector erase suspend/resume suspend the erase operation to allow a read operation in another sector within the same device general description amds 5.0 v-only flash memory pc card provides the highest system level performance for data and file stor- age solutions to the portable pc market segment. man- ufactured with amds negative gate erase, 5.0 v-only technology, the amd 5.0 v-only flash memory cards are the most cost-effective and reliable approach to single-supply flash memory cards. data files and ap- plication programs can be stored on the c series cards. this allows oem manufacturers of portable sys- tems to eliminate the weight, high power consumption and reliability issues associated with electromechanical disk-based systems. the c series cards also allow to- days bulky and heavy battery packs to be reduced in weight and size. typically only two aa alkaline batter- ies are required for total system operation. amds flash memory pc cards provide the most efficient method to transfer useful work between different hard- ware platforms. the enabling technology of the c se- ries cards enhances the productivity of mobile workers. widespread acceptance of the c series cards is as- sured due to their compatibility with the 68-pin pcm- cia/jeida international standard. amds flash memory cards can be read in either a byte-wide or word-wide mode which allows for flexible integration into various system platforms. compatibility is assured at the hardware interface and software interchange specification. the card information structure (cis) or metaformat, can be written by the oem at the memory cards attribute memory address space beginning at address 00000h by using a format utility. the cis ap- pears at the beginning of the cards attribute memory space and defines the low-level organization of data on the pc card. the c series cards contains a separate 512 byte eeprom memory for the cards attribute memory space. this allows all of the flash memory to be used for the common memory space. third party software solutions such as microsofts flash file system (ffs), m-systems true ffs, and scms scm-ffs, enable amds flash memory pc card to replicate the function of traditional disk-based memory systems.
2 amc0xxcflka 5/4/98 block diagram notes: r = 20 k(min)/140 k w (max) *1 mbyte card = s0 + s1, *2 mbyte card = s0s3, *4 mbyte card = s0s7, *10 mbyte card = s0s19 address buffers and decoders i/o transceivers and buffers wp (note 1) a0Ca8 d0Cd7 attribute memory ce write protect switch v cc a0Ca18 ceh 0C ceh 9 cel 0C cel 9 d0Cd15 we oe wp d8Cd15 d0Cd7 we oe a0 a1Ca23* ce 2 ce 1 a1Ca9 a0 ce 2 ce 1 reg cd 1 cd 2 card detect bvd 1 bvd 2 v cc battery voltage detect gnd v cc 10k v cc rr r decoder v cc rr am29f040 a0Ca18 d0Cd7 ce we oe v ss v cc s0* am29f040 a0Ca18 d8Cd15 ce we oe v ss v cc s1* a0Ca18 d0Cd7 ce we oe v ss v cc s2* a0Ca18 d8Cd15 ce we oe v ss v cc s3* a0Ca18 d0Cd7 ce we oe v ss v cc s18* a0Ca18 d8Cd15 ce we oe v ss v cc s19* 18723c-1 5/4/98 amc0xxcflka 3 pc card pin assignments notes: i = input to card, o = output from card i/o = bidirectional nc = no connect in systems which switch v cc individually to cards, no signal should be directly connected between cards other than ground. 1. v pp not required for programming or reading operations. 2. bvd = internally pulled-up. 3. signal must not be connected between cards. 4. highest address bit for 1 mbyte card. 5. highest address bit for 2 mbyte card. 6. highest address bit for 4 mbyte card. 7. highest address bit for 10 mbyte card. pin# 3 3 function pin# signal i/o function 1 gnd ground 35 gnd ground 2 d3 i/o data bit 3 36 cd 1 o card detect 1 (note 3) 3 d4 i/o data bit 4 37 d11 i/o data bit 11 4 d5 i/o data bit 5 38 d12 i/o data bit 12 5 d6 i/o data bit 6 39 d13 i/o data bit 13 6 d7 i/o data bit 7 40 d14 i/o data bit 14 7ce 1 i card enable 1 (note 3) 41 d15 i/o data bit 15 8 a10 i address bit 10 42 ce 2 i card enable 2 (note 3) 9oe i output enable 43 nc no connect 10 a11 i address bit 11 44 nc no connect 11 a9 i address bit 9 45 nc no connect 12 a8 i address bit 8 46 a17 i address bit 17 13 a13 i address bit 13 47 a18 i address bit 18 14 a14 i address bit 14 48 a19 i address bit 19 (note 4) 15 we i write enable 49 a20 i address bit 20 (note 5) 16 nc no connect 50 a21 i address bit 21 (note 6) 17 v cc1 power supply 51 v cc2 power supply 18 nc no connect (note 1) 52 nc no connect (note 1) 19 a16 i address bit 16 53 a22 i address bit 22 20 a15 i address bit 15 54 a23 i address bit 23 (note 7) 21 a12 i address bit 12 55 nc no connect 22 a7 i address bit 7 56 nc no connect 23 a6 i address bit 6 57 nc no connect 24 a5 i address bit 5 58 nc no connect 25 a4 i address bit 4 59 nc no connect 26 a3 i address bit 3 60 nc no connect 27 a2 i address bit 2 61 reg i register select 28 a1 i address bit 1 62 bvd 2 o battery voltage detect 2 (note 2) 29 a0 i address bit 0 63 bvd 1 o battery voltage detect 1 (note 2) 30 d0 i/o data bit 0 64 d8 i/o data bit 8 31 d1 i/o data bit 1 65 d9 i/o data bit 9 32 d2 i/o data bit 2 66 d10 i/o data bit 10 33 wp o write protect (note 3) 67 cd 2 o card detect 2 (note 3) 34 gnd ground 68 gnd ground 4 amc0xxcflka 5/4/98 ordering information standard products amd standard products are available in several packages and operating ranges. the order number (valid combination) is formed by a combination of: speed option -150 ns output configuration: (x16/x8) flash technology pc memory card memory card density 001 = one megabyte 002 = two megabyte 004 = four megabyte 010 = ten megabyte amd revision level series am c 0xx c fl k axxx 5/4/98 amc0xxcflka 5 pin description a0Ca23 address inputs these inputs are internally latched during write cycles. bvd 1, bvd 2 battery voltage detect internally pulled-up. cd 1, cd 2 card detect when card detect 1 and 2 = ground the system detects the card. ce 1, ce 2 card enable this input is active low. the memory card is deselected and power consumption is reduced to standby levels when ce is high. ce activates the internal memory card circuitry that controls the high and low byte control logic of the card, input buffers segment decoders, and associated memory devices. d0Cd15 data input/output data inputs are internally latched on write cycles. data outputs during read cycles. data pins are active high. when the memory card is deselected or the outputs are disabled the outputs float to tristate. gnd ground nc no connect corresponding pin is not connected internally to the die. oe output enable this input is active low and enables the data buffers through the card outputs during read cycles. reg attribute memory select this input is active low and enables reading the cis from the eeprom. v cc pc card power supply for device operation (5.0 v 5%). we write enable this input is active low and controls the write function of the command register to the memory array. the target address is latched on the falling edge of the we pulse and the appropriate data is latched on the rising edge of the pulse. wp write protect this output is active high and disables all card write operations. memory card operations the c series flash memory card is organized as an array of individual devices. each device is 512k bytes in size with eight 64k byte sectors. although the ad- dress space is continuous each physical device defines a logical address segment size. byte-wide erase operations could be performed in four ways: n in increments of the segment size n in increments of the sectors in individual segments n all eight sectors in parallel within individual segments n selected sectors of the eight sectors in parallel within individual segments multiple segments may be erased concurrently when additional i cc current is supplied to the device. once a memory sector or memory segment is erased any ad- dress location may be programmed. flash technology allows any logical 1 data bit to be programmed to a logical 0. the only way to reset bits to a logical 1 is to erase the entire memory sector of 64k bytes or memory segment of 512k bytes. erase operations are the only operations that work on entire memory sectors or memory segments. all other operations such as word-wide programming are not af- fected by the physical memory segments. the common memory space data contents are altered in a similar manner as writing to individual flash mem- ory devices. on-card address and data buffers activate the appropriate flash device in the memory array. each device internally latches address and data during write cycles. refer to table 1. attribute memory is a separately accessed card mem- ory space. the register memory space is active when the reg pin is driven low. the card information struc- ture (cis) describes the capabilities and specification of a card. the cis is stored in the attribute memory space beginning at address 00000h. the c series cards contain a separate 512 byte eeprom memory for the card information structure. d0Cd7 are active during attribute memory accesses. d8Cd15 should be ignored. odd order bytes present invalid data. refer to ta b l e 2 . 6 amc0xxcflka 5/4/98 word-wide operations the c series cards provide the flexibility to operate on data in a byte-wide or word-wide format. in word-wide operations the low-bytes are controlled with ce 1 when a0 = 0. the high-bytes are controlled with ce 2 with a0 = dont care. table 1. common memory bus operations legend: x = dont care, where dont care is either at v il or v ih level. see dc characteristics for voltage levels of normal ttl or cmos input levels. notes: 1. v pp pins are not connected in the 5.0 v-only flash memory card. 2. manufacturer and device codes may be accessed via a command register write sequence. (refer to autoselect command in tables 3 and 4.) 3. standby current is i ccs . 4. refer to tables 3 and 4 for valid d in during a byte write operation. 5. refer to table 5 for valid d in during a word write operation. 6. byte accesseven. in this x8 mode, a0 = v il outputs or inputs the even byte (low byte) of the x16 word on d0Cd7. 7. byte accessodd. in this x8 mode, a0 = v ih outputs or inputs the odd byte (high byte) of the x16 word on d0Cd7. this is accomplished internal to the card by transposing d8Cd15 to d0Cd7. 8. odd byte only access. in this x8 mode, a0 = x outputs or inputs the odd byte (high byte) of the x16 word on d8Cd15. 9. x16 word accesses present both even (low) and odd (high) bytes. a0 = x. pins/operation reg ce 2ce 1oe we a0 d8Cd15 d0Cd7 read-only read (x8) (note 6) v ih v ih v il v il v ih v il high-z data out-even read (x8) (note 7) v ih v ih v il v il v ih v ih high-z data out-odd read (x8) (note 8) v ih v il v ih v il v ih x data out-odd high-z read (x16) (note 9) v ih v il v il v il v ih x data out-odd data out-even output disable v ih xxv ih v ih x high-z high-z standby (note 3) x v ih v ih x x x high-z high-z read/write read (x8) (notes 2, 6) v ih v ih v il v il v ih v il high-z data out-even read (x8) (notes 2, 7) v ih v ih v il v il v ih v ih high-z data out-odd read (x8) (notes 2, 8) v ih v il v ih v il v ih x data out-odd high-z read (x16) (notes 2, 9) v ih v il v il v il v ih x data out-odd data out-even write (x8) (notes 4, 6) v ih v ih v il v ih v il v il high-z data in-even write (x8) (notes 4, 7) v ih v ih v il v ih v il v ih high-z data in-odd write (x8) (notes 4, 8) v ih v il v ih v ih v il x data in-odd high-z write (x16) (notes 5, 9) v ih v il v il v ih v il x data in-odd data in-even output disable v ih xxv ih v il x high-z high-z standby (note 3) x v ih v ih x x x high-z high-z volt-only? 5/4/98 amc0xxcflka 7 table 2. attribute memory bus operations legend: x = dont care, where dont care is either v il or v ih levels. see dc characteristics for voltage levels of normal ttl or cmos input levels. notes: 1. v pp pins are not connected in the 5.0 v-only flash memory card. 2. in this x8 mode, a0 = v il outputs or inputs the even byte (low byte) of the x16 word on d0Cd7. 3. only even-byte data is valid during attribute memory read function. 4. during attribute memory read function, reg and oe must be active for the entire cycle. 5. during attribute memory write function, reg and we must be active for the entire cycle, oe must be inactive for the entire cycle. 6. standby current is i ccs . pins/operation reg ce 2ce 1oe we a0 d8Cd15 d0Cd7 read-only read (x8) (notes 2, 4) v il v ih v il v il v ih v il high-z data out-even read (x8) (notes 3, 4) v il v ih v il v il v ih v ih high-z not valid read (x8) (note 3) v il v il v ih v il v ih x not valid high-z read (x16) (notes 3, 4, 5) v il v il v il v il v ih x not valid data out-even output disable v il xxv ih v ih x high-z high-z standby (note 6) x v ih v ih x x x high-z high-z read/write read (x8) (notes 2, 4) v il v ih v il v il v ih v il high-z data out-even read (x8) (notes 3, 4) v il v ih v il v il v ih v ih high-z not valid read (x8) (note 4) v il v il v ih v il v ih x not valid high-z read (x16) (note 4) v il v il v il v il v ih x not valid data out-even write (x8) (notes 2, 5) v il v ih v il v ih v il v il high-z data in-even write (x8) (note 5) v il v ih v il v ih v il v ih high-z high-z write (x8) (notes 4, 5) v il v il v ih v ih v il x high-z high-z write (x16) (note 5) v il v il v il v ih v il x high-z data in-even output disable v il xxv ih v il x high-z high-z standby (note 6) x v ih v ih x x x high-z high-z volt-only? 8 amc0xxcflka 5/4/98 byte-wide operations byte-wide data is available on d0Cd7 for read and write operations (ce 1 = low, ce 2 = high). even and odd bytes are stored in separate memory segments (i.e., s0 and s1) and are accessed when a0 is low and high respectively. the even byte is the low order byte and the odd byte is the high order byte of a 16-bit word. erase operations in the byte-wide mode must account for data multiplexing on d0Cd7 by changing the state of a0. each memory sector or memory segment pair must be addressed separately for erase operations. card detection each cd (output) pin should be read by the host sys- tem to determine if the memory card is adequately seated in the socket. cd 1 and cd 2 are internally tied to ground. if both bits are not detected, the system should indicate that the card must be reinserted. write protection the amd flash memory card has three types of write protection. the pcmcia/jeida socket itself provides the first type of write protection. power supply and con- trol pins have specific pin lengths in order to protect the card with proper power supply sequencing in the case of hot insertion and removal. a mechanical write protect switch provides a second type of write protection. when this switch is activated, we is internally forced high. the flash memory com- mand register is disabled from accepting any write commands. the third type of write protection is achieved with v cc1 and v cc2 below v lko . each flash memory device that comprises a flash memory segment will reset the com- mand register to the read-only mode when v cc is below v lko . v lko is the voltage below which write op- erations to individual command registers are disabled. memory card bus operations read enable two card enable (ce ) pins are available on the mem- ory card. both ce pins must be active low for word-wide read accesses. only one ce is required for byte-wide accesses. the ce pins control the selection and gates power to the high and low memory seg- ments. the output enable (oe ) controls gating ac- cessed data from the memory segment outputs. the device will automatically power-up in the read/ reset state. in this case, a command sequence is not required to read data. standard microprocessor read cycles will retrieve array data. this default value en- sures that no spurious alteration of the memory content occurs during the power transition. refer to the ac read characteristics and waveforms for the specific timing parameters. output disable data outputs from the card are disabled when oe is at a logic-high level. under this condition, outputs are in the high-impedance state. standby operations byte-wide read accesses only require half of the read/ write output buffer (x16) to be active. in addition, only one memory segment is active within either the high order or low order bank. activation of the appropriate half of the output buffer is controlled by the combination of both ce pins. the ce pins also control power to the high and low-order banks of memory. outputs of the memory bank not selected are placed in the high im- pedance state. the individual memory segment is acti- vated by the address decoders. the other memory segments operate in standby. an active memory seg- ment continues to draw power until completion of a write or erase operation if the card is deselected in the process of one of these operations. auto select operation a host system or external card reader/writer can deter- mine the on-card manufacturer and device i.d. codes. codes are available after writing the 90h command to the command register of a memory segment per tables 3 and 4. reading from address location 00000h in any segment provides the manufacturer i.d. while address location 00002h provides the device i.d. to terminate the auto select operation, it is necessary to write the read/reset command sequence into the register. write operations write and erase operations are valid only when v cc1 and v cc2 are above 4.75 v. this activates the state machine of an addressed memory segment. the com- mand register is a latch which saves address, com- mands, and data information used by the state machine and memory array. when write enable (we ) and appropriate ce (s) are at a logic-level low, and output enable (oe ) is at a logic-high, the command register is enabled for write operations. the falling edge of we latches address in- formation and the rising edge latches data/command information. write or erase operations are performed by writing ap- propriate data patterns to the command register of ac- cessed flash memory sectors or memory segments. the byte-wide and word-wide commands are defined in tables 3, 4, and 5, respectively. 5/4/98 amc0xxcflka 9 table 3. even byte command definitions (note 5) * address for memory segment 0 (s0) only. address for the higher even memory segments (s2Cs18) = (addr) + (n/2)* 100000h where n = memory segment number (0) for 1 mbyte, n = (0, 2) for 2 mbyte, n = (0, 2, 4, 6) for 4 mbyte, n = (018) for 10 mbyte. notes: 1. address bit a16 = x = dont care for all address commands except for program address (pa), read address (ra) and sector address (sa). 2. bus operations are defined in table 1. 3. ra = address of the memory location to be read. pa = address of the memory location to be programmed. addresses are latched on the falling edge of the we pulse. sa = address of the sector to be erased. the combination of a17, a18, a19 will uniquely select any sector of a segment. to select the memory segment:1 and 2 mbyte: use ce 1 and a20 4 mbyte: use ce 1 and a20, a21 10 mbyte: use ce 1 and a20Ca23. 4. rd = data read from location ra during read operation. pd = data to be programmed at location pa. data is latched on the rising edge of we pulse. 5. a0 = 0 and ce 1 = 0 embedded command sequence bus write cycles reqd first bus write cycle second bus write cycle third bus write cycle fourth bus read/write cycle fifth bus write cycle sixth bus write cycle addr* data addr* data addr* data addr* data addr* data addr* data reset/read 4 aaaah aah 5554h 55h aaaah f0h ra rd autoselect 4 aaaah aah 5554h 55h aaaah 90h 00h/02h 01h/a4h byte write 4 aaaah aah 5554h 55h aaaah a0h pa pd segment erase 6 aaaah aah 5554h 55h aaaah 80h aaaah aah 5554h 55h aaaah 10h sector erase 6 aaaah aah 5554h 55h aaaah 80h aaaah aah 5554h 55h sa 30h sector erase suspend erase can be suspended during sector erase with addr (dont care), data (b0h) sector erase resume erase can be resumed after suspend with addr (dont care), data (30h) 10 amc0xxcflka 5/4/98 table 4. odd byte command definitions (note 5) *address for memory segment 1 (s1) only. address for the higher odd memory segments (s3Cs19) = (addr) + ((nC1)/2)* 100000h + 80000h where n = memory segment number (1) for 1 mbyte, n = (1, 3) for 2 mbyte, n = (1, 3, 5, 7) for 4 mbyte, n = (119) for 10 mbyte. notes: 1. address bit a16 = x = dont care for all address commands except for program address (pa), read address (ra) and sector address (sa). 2. bus operations are defined in table 1. 3. ra = address of the memory location to be read. pa = address of the memory location to be programmed. addresses are latched on the falling edge of the we pulse. sa = address of the sector to be erased. the combination of a17, a18, a19 will uniquely select any sector of a segment. to select the memory segment:1 and 2 mbyte: use ce 2 and a20 4 mbyte: use ce 2 and a20, a21 10 mbyte: use ce 2 and a20Ca23. 4. rd = data read from location ra during read operation. pd = data to be programmed at location pa. data is latched on the rising edge of we pulse. 5. a0 = 1 and ce 1 = 0 or a0 = x and ce 2 = 0. embedded command sequence bus write cycles reqd first bus write cycle second bus write cycle third bus write cycle fourth bus read/write cycle fifth bus write cycle sixth bus write cycle addr* data addr* data addr* data addr* data addr* data addr* data reset/read 4 aaabh aah 5555h 55h aaabh f0h ra rd autoselect 4 aaabh aah 5555h 55h aaabh 90h 00h/02h 01h/a4h byte write 4 aaabh aah 5555h 55h aaabh a0h pa pd segment erase 6 aaabh aah 5555h 55h aaabh 80h aaabh aah 5555h 55h aaabh 10h sector erase 6 aaabh aah 5555h 55h aaabh 80h aaabh aah 5555h 55h sa 30h sector erase suspend erase can be suspended during sector erase with addr (dont care), data (b0h) sector erase resume erase can be resumed after suspend with addr (dont care), data (30h) 5/4/98 amc0xxcflka 11 table 5. word command definitions (note 7) notes: 1. address bit a16 = x = dont care for all address commands except for program address (pa) and sector address (sa). 2. bus operations are defined in table 1. 3. ra = address of the memory location to be read. pa = address of the memory location to be programmed. addresses are latched on the falling edge of the we pulse. sa = address of the sector to be erased. the combination of a17, a18, a19 will uniquely select any sector of a segment. to select the memory segment:1 and 2 mbyte: use ce 1, ce 2, a20 4 mbyte: use ce 1, ce 2, a20, a21 0 mbyte: use ce 1, ce 2, a20Ca23. 4. rw = data read from location ra during read operation. (word mode). pw = data to be programmed at location pa. data is latched on the rising edge of we . (word mode). 5. address for memory segment pair 0 (s0 and s1) only. address for the higher memory segment pairs (s2, s3 = pair 1, s4, s5 = pair 2, s6, s7 = pair 3) is equal to (addr) + m* (80000h) where m = memory segment pair number. 6. word = 2 bytes = odd byte and even byte. 7. ce 1 = 0 and ce 2 = 0. table 6. memory sector address table for memory segment s0 flash memory write/erase operations details of amds embedded write and erase operations embedded erase? algorithm the automatic memory sector or memory segment erase does not require the device to be entirely prepro- gramming prior to executing the embedded erase command. upon executing the embedded erase com- mand sequence, the addressed memory sector or memory segment will automatically write and verify the entire memory segment or memory sector for an all zero data pattern. the system is not required to pro- vide any controls or timing during these operations. when the memory sector or memory segment is auto- matically verified to contain an all zero pattern, a self-timed chip erase-and-verify begins. the erase and verify operations are complete when the data on d7 of the memory sector or memory segment is 1 (see write operation status section) at which time the embedded command sequence bus write cycles reqd first bus write cycle second bus write cycle third bus write cycle fourth bus read/write cycle fifth bus write cycle sixth bus write cycle addr* data addr* data addr* data addr* data addr* data addr* data reset/read 4 aaaah aaaa 5554h 5555 aaaah f0f0 ra rw autoselect 4 aaaah aaaa 5554h 5555 aaaah 9090 00h/02h 0101/ a4a4 byte write 4 aaaah aaaa 5554h 5555 aaaah a0a0 pa pw segment erase 6 aaaah aaaa 5554h 5555 aaaah 8080 aaaah aaaa 5554h 5555 aaaah 1010 sector erase 6 aaaah aaaa 5554h 5555 aaaah 8080 aaaah aaaa 5554h 5555 sa 3030 sector erase suspend erase can be suspended during sector erase with addr (dont care), data (b0h) sector erase resume erase can be resumed after suspend with addr (dont care), data (30h) sector a19 a18 a17 address range 0 0 0 0 00000h-0ffffh 1 0 0 1 10000h-1ffffh 2 0 1 0 20000h-2ffffh 3 0 1 1 30000h-3ffffh 4 1 0 0 40000h-4ffffh 5 1 0 1 50000h-5ffffh 6 1 1 0 60000h-6ffffh 7 1 1 1 70000h-7ffffh note: a0 is not mapped internally. 12 amc0xxcflka 5/4/98 device returns to the read mode (d15 on the odd byte). the system is not required to provide any control or timing during these operations. a reset command after the device has begun execution will stop the de- vice but the data in the operated segment will be unde- fined. in that case, restart the erase on that sector and allow it to complete. when using the embedded erase algorithm, the erase automatically terminates when adequate erase margin has been achieved for the memory array (no erase ver- ify command is required). the margin voltages are in- ternally generated in the same manner as when the standard erase verify command is used. the embedded erase command sequence is a com- mand only operation that stages the memory sector or memory segment for automatic electrical erasure of all bytes in the array. the automatic erase begins on the rising edge of the we and terminates when the data on d7 of the memory sector or memory segment is 1 (see write operation status section) at which time the device returns to the read mode. please note that for the memory segment or memory sector erase oper- ation, data polling may be performed at any address in that segment or sector. figure 1 and table 7 illustrate the embedded erase al- gorithm, a typical command string and bus operations. as described earlier, once the memory sector in a de- vice or memory segment completes the embedded erase operation it returns to the read mode and ad- dresses are no longer latched. therefore, the device requires that a valid address input to the device is sup- plied by the system at this particular instant of time. otherwise, the system will never read a 1 on d7. a system designer has two choices to implement the em- bedded erase algorithm: 1. the system (cpu) keeps the sector address (within any of the sectors being erased) valid during the en- tire embedded erase operation, or 2. once the system executes the embedded erase command sequence, the cpu takes away the ad- dress from the device and becomes free to do other tasks. in this case, the cpu is required to keep track of the valid sector address by loading it into a tem- porary register. when the cpu comes back for per- forming data polling, it should reassert the same address. since the embedded erase operation takes a signifi- cant amount of time (1.5C30 s), option 2 makes more sense. however, the choice of these two options has been left to the system designer. sector erase sector erase is a six bus cycle operation. there are two unlock write cycles. these are followed by writing the set-up command. two more unlock write cycles are then followed by the sector erase command. the sector address (any address location within the desired sec- tor) is latched on the falling edge of we , while the com- mand (data) is latched on the rising edge of we . a time-out of 100 m s from the rising edge of the last sec- tor erase command will initiate the sector erase command(s). multiple sectors may be erased concurrently by writing the six bus cycle operations as described above. this sequence is followed with writes of the sector erase command 30h to addresses in other sectors desired to be concurrently erased. a time-out of 100 m s from the rising edge of the we pulse for the last sector erase command will initiate the sector erase. if another sector erase command is written within the 100 m s time-out window the timer is reset. any command other than sector erase within the time-out window will reset the device to the read mode, ignoring the previous com- mand string (refer to write operation status section for sector erase timer operation). loading the sector erase buffer may be done in any sequence and with anysector number. sector erase does not require the user to program the device prior to erase. the device automatically pro- grams all memory locations in the sector(s) to be erased prior to electrical erase. when erasing a sector table 7. embedded erase algorithm bus operation command comments standby wait for v cc ramp write embedded erase command sequence 6 bus cycle operation read data polling to verify erasure 18723c-2 figure 1. embedded erase algorithm write embedded erase command sequence (table 3 and 4) data poll from device (figure 3) start erasure complete 5/4/98 amc0xxcflka 13 or sectors the remaining unselected sectors are not af- fected. the system is not required to provide any con- trols or timings during these operations. a reset command after the device has begun execution will stop the device but the data in the operated segment will be undefined. in that case, restart the erase on that sector and allow it to complete. the automatic sector erase begins after the 100 m s time out from the rising edge of the we pulse for the last sector erase command pulse and terminates when the data on d7 is 1 (see write operation status sec- tion) at which time the device returns to read mode. data polling must be performed at an address within any of the sectors being erased. figure 1 illustrates the embedded erase algorithm using typical command strings and bus operations. embedded program? algorithm the embedded program setup is a four bus cycle op- eration that stages the addressed memory sector or memory segment for automatic programming. once the embedded program setup operation is per- formed, the next we pulse causes a transition to an ac- tive programming operation. addresses are internally latched on the falling edge of the we pulse. data is in- ternally latched on the rising edge of the we pulse. the rising edge of we also begins the programming opera- tion. the system is not required to provide further con- trol or timing. the device will automatically provide an adequate internally generated write pulse and verify margin. the automatic programming operation is com- pleted when the data on d7 of the addressed memory sector or memory segment is equivalent to data written to this bit (see write operation status section) at which time the device returns to the read mode (no write ver- ify command is required). addresses are latched on the falling edge of we during the embedded program command execution and hence the system is not required to keep the addresses stable during the entire programming operation. how- ever, once the device completes the embedded pro- gram operation, it returns to the read mode and addresses are no longer latched. therefore, the device requires that a valid address input to the device is sup- plied by the system at this particular instant of time. otherwise, the system will never read a valid data on d7. a system designer has two choices to implement the embedded programming algorithm: 1. the system (cpu) keeps the address valid during the entire embedded programming operation, or 2. once the system executes the embedded program- ming command sequence, the cpu takes away the address from the device and becomes free to do other tasks. in this case, the cpu is required to keep track of the valid address by loading it into a temporary register. when the cpu comes back for performing data polling, it should reassert the same address. however, since the embedded programming operation takes only 16 m s typically, it may be easier for the cpu to keep the address stable during the entire embedded programming operation instead of reasserting the valid address during data polling. anyway, this has been left to the system designers choice to go for either opera- tion. any commands written to the segment during this period will be ignored. figure 2 and table 8 illustrate the embedded program algorithm, a typical command string, and bus operation. reset command the reset command initializes the sector or segment to the read mode. please refer to tables 3 and 4, byte command definitions, and table 5, word command definitions for the reset command operation. the sector or segment remains enabled for reads until the command register contents are altered. there is a 6 m s write recovery time before read for the first read after a write. the reset command will safely reset the segment memory to the read mode. memory contents are not altered. following any other command, write the reset command once to the segment. this will safely abort any operation and reset the device to the read mode. the reset is needed to terminate the auto select oper- ation. it can be used to terminate an erase or sector erase operation, but the data in the sector or segment being erased would then be undefined. write operation status data pollingd7 (d15 on odd byte) the flash memory pc card features data polling as a method to indicate to the host system that the embed- ded algorithms are either in progress or completed. while the embedded programming algorithm is in op- eration, an attempt to read the device will produce the complement of expected valid data on d7 of the ad- dressed memory sector or memory segment. upon table 8. embedded program algorithm bus operation command comments standby wait for v cc ramp write embedded program command sequence 3 bus cycle operation write program address/data 1 bus cycle operation read data polling to verify program 14 amc0xxcflka 5/4/98 completion of the embedded program algorithm an at- tempt to read the device will produce valid data on d7. the data polling feature is valid after the rising edge of the fourth we pulse of the four write pulse sequence. while the embedded erase algorithm is in operation, d7 will read 0 until the erase operation is completed. upon completion of the erase operation, the data on d7 will read 1. the data polling feature is only active during the em- bedded programming or erase algorithms. please note that the amc0xxcflka data pin (d7) may change asynchronously while output enable (oe ) is asserted low. this means that the device is driving status infor- mation on d7 at one instant of time and then the bytes valid data at the next instant of time. depending on when the system samples the d7 output, it may read ei- ther the status or valid data. even if the device has completed the embedded operation and d7 has a valid data, the data outputs on d0Cd6 may be still invalid since the switching time for data bits (d0Cd7) will not be the same. this happens since the internal delay paths for data bits (d0Cd7) within the device are differ- ent. the valid data will be provided only after a certain time delay ( 16 amc0xxcflka 5/4/98 write operation status table 9. hardware sequence flags note: d0, d1, and d2 are reserve pins for future use. d4 is for amd internal use only. status d7d6d5d3 d2Cd0 in progress auto-programming d 7 toggle 0 0 programming in auto-erase 0 toggle 0 1 (d ) erasing in auto-erase 0 toggle 0 1 exceeded time limits auto-programming d 7 toggle 1 0 programming in auto-erase 0 toggle 1 1 (d ) erasing in auto-erase 0 toggle 1 1 start fail no d7 = data? no pass ye s no ye s d7 = data? d5 = 1? ye s read byte (d0Cd7) addr = va read byte (d0Cd7) addr = va 18723c-4 note: d7 is rechecked even if d5 = 1 because d7 may change simultaneously with d5. figure 3. data polling algorithm va = valid address va = byte addr for write operation va = any segment (sector) address during segment (sector) erase operation 5/4/98 amc0xxcflka 17 start fail ye s d6 = toggle? ye s pass no no ye s d6 = toggle? d5 = 1? no read byte (d0Cd7) addr = va read byte (d0Cd7) addr = va 18723c-5 note: d6 is rechecked even if d5 = 1 because d6 may stop toggling at the same time as d5 changes to 1. figure 4. toggle bit algorithm va = valid address va = byte addr for write operation va = any segment (sector) address during segment (sector) erase operation 18 amc0xxcflka 5/4/98 18723c-6 * d7 = valid data (the device has completed the embedded operation.) figure 5. ac waveforms for data polling during embedded algorithm operations d0Cd6 valid data t oe d7 = valid data high-z ce oe we d7 d 7 d0Cd6 d0Cd6 = invalid * t oeh t ce t ch t df t oh t whwh 3 or 4 18723c-7 * d6 stops toggling (the device has completed the embedded operation.) figure 6. ac waveforms for toggle bit during embedded algorithm operations ce t oeh we oe d6 = stop toggling d0Cd7 valid d6 = toggle d6 = toggle data (d0Cd7) * t oe 5/4/98 amc0xxcflka 19 embedded algorithms 18723c-8 figure 7. byte-wide programming and erasure overview software polling from memory segment write embedded programming or erase command sequence to memory segments completed the embedded algorithm operations completely automate the programming and erase procedure by internally exe- cuting the algorithmic command sequence of original amd devices. the devices automatically provide write opera- tion status information with standard read operations. see table 3 or 4 for program command sequence. start 20 amc0xxcflka 5/4/98 embedded algorithms 18723c-9 figure 8. byte-wide programming flow chart activity initialize programming variables: ef = error flag pgm =embedded byte write command sequence cycle #1C3 (table 3 or 4) adrs = appropriate address for memory segment pd = program data vdat = valid data fmd = flash memory data ef = 0 = no programming error ef = 1 = programming error program complete initialization: ef = 0 wait 16 m s read adrs/fmd program error begin programming write pgm get adrs/pd vdat = pd write adrs/pgm write adrs/vdat no ye s ye s ye s no fmd = vdat no fmd = vdat more data begin software polling subroutine (figure 9) 5/4/98 amc0xxcflka 21 embedded algorithms d5 = 1? 18723c-10 note: d7 is checked even if d5 = 1 because d7 may have changed simultaneously with d5 or immediately after d5. figure 9. byte-wide software polling for programming subroutine va = byte address for programming d5 = 1 no = program time not exceeded limit yes = program time exceed limit, device failed ef = error flag start subroutine no ye s ye s ye s no d7 = data? no d7 = data subroutine return recommend 16 m s time out from previous data polling device failed to program ef = 1 device passed read byte (d0Cd7) addr = va read byte (d0Cd7) addr = va 22 amc0xxcflka 5/4/98 embedded algorithms 18723c-11 figure 10. byte-wide erasure flow chart activity ef = error flag = 0 seg adrs = segment address = 0 ers =erase command sequence (even byte per table 3, odd byte per table 4) 3 seconds wait = 2 seconds memory segment preprogram time +1 second memory segment erase time fmd = flash memory data ffh = erased flash memory data erase complete wait 3 seconds erase error begin erase no ye s ye s ye s no fmd = ffh no fmd = ffh last segment address initialization: ef = 0 seg adrs = 0 write ers cycle #1C5 write segadrs/ers cycle #6 read seg adrs/fmd begin software polling subroutine (figure 11) increment seg adrs 5/4/98 amc0xxcflka 23 embedded algorithms d5 = 1? 18723c-12 figure 11. byte-wide software polling erase subroutine x = dont care d7 = 1 yes = erase complete no = erase not complete d5 = 1 yes = erase time exceeded limit, device failed no = erase time has not exceeded limit start subroutine no ye s ye s ye s no d7 = 1? no d7 = 1 subroutine return device failed to program ef = 1 device passed read byte (d0Cd7) addr = x read byte (d0Cd7) addr = x 24 amc0xxcflka 5/4/98 word-wide programming and erasing word-wide programming the word-wide programming sequence will be as usual per table 5. the program word command is a0a0h. each byte is independently programmed. for example, if the high byte of the word indicates the suc- cessful completion of programming via one of its write status bits such as d15, software polling should con- tinue to monitor the low byte for write completion and data verification, or vice versa. during the embedded programming operations the device executes program- ming pulses in 16 m s increments. status reads provide information on the progress of the byte programming relative to the last complete write pulse. status informa- tion is automatically updated upon completion of each internal write pulse. status information does not change within the 16 m s write pulse width. word-wide erasing the word-wide erasing of a memory segment pair is similar to word-wide programming. the erase word command is a 6 bus cycle command sequence per table 5. each byte is independently erased and veri- fied. word-wide erasure reduces total erase time when compared to byte erasure. each flash memory device in the card may erase at different rates. therefore each device (byte) must be verified separately. 18723c-13 figure 12. embedded algorithm word-wide programming and erasure overview software polling from memory segments write embedded programming or erase command sequence to memory segments completed the embedded algorithm operations completely automate the parallel programming and erase procedures by inter- nally executing the algorithmic command sequences of amds flashrite and flasherase algorithms. the devices automatically provide write operation status information with standard read operations. see table 5 for program command sequence. start 5/4/98 amc0xxcflka 25 embedded algorithms 18723c-14 figure 13. word-wide programming flow chart activity initialize programming variables: ef = error flag ef = 0 = no failure ef = 1 = low byte program error ef = 2 = high byte program error ef = 3 = word-wide program error vwdat = valid word data pgm =embedded word write command sequence cycle #1C3 (table 5) adrs = appropriate address for memory segment (cycle #4) pdw = program data word fmd = flash memory data program complete initialization: ef = 0 program error begin programming no ye s ye s ye s no fmd = vwdat no fmd = vwdat more data get adrs/pdw vwdat = pdw write pgm write adrs/pdw wait 16 m s read adrs/fmd begin software polling subroutine (figure 14) 26 amc0xxcflka 5/4/98 embedded algorithms 18723c-15 figure 14. word-wide software polling program subroutine va = word address for programming v data = valid data d5/13 = 1? yes = erase time has exceeded limit, device failed no = erase time has not exceeded limit start subroutine ye s no d7 = v data ? ye s d15 = v data ? subroutine return low byte program time exceeded limit, ef = 1 read byte (d0Cd7) addr = va read byte (d8Cd15) addr = va no d5 = 1? read byte (d0Cd7) addr = va ye s no d7 = v data ? no no d13 = 1? read byte (d8Cd15) addr = va no d15 = v data ? ye s ye s high byte program time exceeded limit, ef = 2 + ef ye s 5/4/98 amc0xxcflka 27 embedded algorithms 18723c-16 figure 15. word-wide erasure flow chart activity ef = error flag ef = 0 = no failure ef = 1 = low byte erase error ef = 2 = high byte erase error ef = 3 = word-wide erase error seg adrs = segment address ers = segment erase command sequence (table 5) fmd = flash memory data erase complete wait 3 seconds erase error begin erase no ye s ye s ye s no fmd = ffffh no fmd = ffffh last segment address read seg adrs/fmd begin software polling subroutine (figure 16) increment seg adrs write ers cycle #6: seg adrs initialization: ef = 0 seg adrs = 0 write ers cycle #1C5 28 amc0xxcflka 5/4/98 embedded algorithms 18723c-17 figure 16. word-wide software polling erase subroutine d7/15 = 1 yes = erase complete no = erase not complete d5/13 = 1 yes = erase time has exceeded limit, device failed no = erase time has not exceeded limit start subroutine ye s no d7 = 1? ye s d15 = 1? subroutine return low byte program time exceeded limit, ef = 1 read byte (d0Cd7) read byte (d8Cd15) no d5 = 1? read byte (d0Cd7) ye s no d7 = 1? no no d13 = 1? no d15 = 1? ye s high byte program time exceeded limit, ef = 2 + ef ye s read byte (d8Cd15) ye s 5/4/98 amc0xxcflka 29 absolute maximum ratings storage temperature . . . . . . . . . . . . . C30 c to +70 c ambient temperature with power applied. . . . . . . . . . . . . . . C10 c to +70 c voltage at all pins (note 1) . . . . . . . .C2.0 v to +7.0 v v cc (note 1). . . . . . . . . . . . . . . . . . . . . C0.5 v to 6.0 v output short circuit current (note 2) . . . . . . . 40 ma notes: 1. minimum dc voltage on input or i/o pins is C0.5 v. during voltage transitions, inputs may overshoot v ss to C2.0 v for periods of up to 20 ns. maximum dc voltage on output and i/o pins is v cc + 0.5 v. during voltage transitions, outputs may overshoot to v cc + 2.0 v for periods up to 20ns. 2. no more than one output shorted at a time. durations of the short circuit should not be greater than one second. conditions equal v out = 0.5 v or 5.0 v, v cc = v cc max. these values are chosen to avoid test problems caused by tester ground degradation. this parameter is sampled and not 100% tested, but guaranteed by characterization. 3. v pp1 and v pp2 are not connected. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the op- erational sections of this specification is not implied. expo- sure of the device to absolute maximum rating conditions for extended periods may affect device reliability. operating ranges commercial (c) devices case temperature (t c ). . . . . . . . . . . . . .0 c to +60 c v cc supply voltages. . . . . . . . . . . . +4.75 v to 5.25 v operating ranges define those limits between which the functionality of the device is guaranteed. 30 amc0xxcflka 5/4/98 dc characteristics byte-wide operation notes: 1. for ttl input voltage levels (v il or v ih ), the minimum limit should be increased by: 1 ma for 1 mbyte 3 ma for 2 mbyte 7 ma for 4 mbyte 19 ma for 10 mbyte. 2. one flash device active, all the others in standby. parameter symbol parameter description test description min max unit i li input leakage current v cc = v cc max, v in = v cc or v ss for all cards: (ce , reg , we , oe = C300 m a min) 1 mb C300 + 20 m a 2 mb C300 + 20 4 mb C300 + 20 10 mb C300 + 20 i lo output leakage current v cc = v cc max, v out = v cc or v ss 1 mb 20 m a 2 mb 20 4 mb 20 10 mb 20 i ccs v cc standby current (note 1) v cc = v cc max ce = v cc 0.2 v v in = v cc or gnd 1 mb 0.7 ma 2 mb 0.9 4 mb 1.3 10 mb 2.5 i cc1 v cc active read current (notes 1, 2) v cc = v cc max, ce = v il , oe = v ih , i out = 0 ma, at 3.3 mhz 45 ma i cc2 v cc write/erase current (notes 1, 2) ce = v il programming in progress 65 ma v il input low voltage C0.5 0.8 v v ih input high voltage 2.4 v cc + 0.3 v v ol output low voltage i ol = 3.2 ma, v cc = v cc min 0.40 v v oh output high voltage i oh = 2.0 ma, v cc = v cc min 3.8 v cc v v lko low v cc lock-out voltage 3.2 4.2 v 5/4/98 amc0xxcflka 31 word-wide operation notes: 1. for ttl input voltage levels (v il or v ih ), the minimum limit should be increased by: 2 ma for 2 mbyte 6 ma for 4 mbyte 18 ma for 10 mbyte. 2. two flash devices active, all the others in standby parameter symbol parameter description test description min max unit i li input leakage current v cc = v cc max, v in = v cc or v ss (ce , reg , we , oe = C300 m a min) 1 mb C300 + 20 m a 2 mb C300 + 20 4 mb C300 + 20 10 mb C300 + 20 i lo output leakage current v cc = v cc max, v out = v cc or v ss 1 mb 20 m a 2 mb 20 4 mb 20 10 mb 20 i ccs v cc standby current (note 1) v cc = v cc max ce = v cc 0.2 v v in = v cc or gnd 1 mb 0.7 ma 2 mb 0.9 4 mb 1.3 10 mb 2.5 i cc1 v cc active read current (notes 1, 2) v cc = v cc max, ce = v il , oe = v ih , i out = 0 ma, at 3.3 mhz 90 ma i cc2 v cc programming current (notes 1, 2) ce = v il programming in progress 130 ma v il input low voltage C0.5 0.8 v v ih input high voltage 2.4 v cc + 0.3 v v ol output low voltage i ol = 3.2 ma, v cc = v cc min 0.40 v v oh output high voltage i oh = 2.0 ma, v cc = v cc min 3.8 v cc v v lko low v cc lock-out voltage 3.2 4.2 v 32 amc0xxcflka 5/4/98 pin capacitance notes: 1. sampled, not 100% tested. 2. test conditions t a = 25 c, f = 1.0 mhz. switching ac characteristics read only operation (note 1) note: 1. input rise and fall times (10% to 90%): e 10 ns, input pulse levels: v ol and v oh , timing measurement reference level: inputsv il and v ih outputsv il and v ih parameter symbol parameter description test conditions max unit c in1 all except a1Ca9 v in = 0 v 31 pf c out output capacitance v out = 0 v 31 pf c in2 a1Ca9 v in = 0 v 45 pf c i/o i/o capacitance d0Cd15 v i/o = 0 v 31 pf card speed parameter symbol parameter description -150 ns unit jedec standard min max t avav t rc read cycle time 150 ns t elqv t ce chip enable access time 150 ns t avqv t acc address access time 150 ns t glqv t oe output enable access time 75 ns t elqx t lz chip enable to output in low-z 5 ns t ehqz t df chip disable to output in high-z 75 ns t glqx t olz output enable to output in low-z 5 ns t ghqz t df output disable to output in high-z 75 ns t axqx t oh output hold from first of address, ce , or oe change 5 ns t whgl write recovery time before read 6 m s 5/4/98 amc0xxcflka 33 ac characteristics write/erase/program operations notes: 1. rise/fall e 10 ns. 2. maximum specification not needed due to the devices internal stop timer that will stop any erase or write operation that exce ed the device specification. 3. embedded program operation of 16 m s consist of 10 m s program pulse and 6 m s write recovery before read. this is the minimum time for one pass through the programming algorithm. d5 = 1 only after a byte takes longer than 48 ms to write. card speed parameter symbol parameter description -150 ns unit jedec standard min typ max t avav t wc write cycle time 150 ns t avwl t as address setup time 20 ns t wlax t ah address hold time 55 ns t dvwh t ds data setup time 50 ns t whdx t dh data hold time 20 ns t oeh output enable hold time for embedded algorithm 20 ns t whgl t wr write recovery time before read 6 m s t ghwl read recovery time before write 0 m s t wloz output in high-z from write enable 5 ns t whoz output in low-z from write enable 60 ns t elwl t cs ce setup time 0 ns t wheh t ch ce hold time 20 ns t wlwh t wp write pulse width 45 ns t whwl t wph write pulse width high 50 ns t whwh3 embedded programming operation (notes 1, 2, 3) 16 m s 48 ms t whwh4 embedded erase operation for each 64k byte memory sector (notes 1, 2) 1.5 s t vcs v cc setup time to ce low 50 m s 34 amc0xxcflka 5/4/98 key to switching waveforms switching waveforms must be steady may change from h to l may change from l to h does not apply dont care, any change permitted will be steady will be changing from h to l will be changing from l to h changing, state unknown center line is high- impedance off state waveform inputs outputs ks000010-pal 18723c-18 note: ce refers to ce 1 and ce 2. figure 17. ac waveforms for read operations addresses ce oe we outputs addresses stable high-z high-z (t df ) (t oh ) output valid t acc t oe (t ce ) t rc 5/4/98 amc0xxcflka 35 switching waveforms 18723c-19 note: sa is the sector address for sector erase per table 6. figure 18. ac waveforms segment/sector byte erase operations t as t wp t cs t dh aaaah 5554h sa ce oe we data v cc aah 55h addresses 5554h t vcs t ds aaaah aaaah twph t ghwl t ah aah 55h 80h 10h/30h 36 amc0xxcflka 5/4/98 switching waveforms v cc t vcs 18723c-20 notes: 1. figure indicates last two bus cycles of four bus cycle sequence. 2. pa is address of the memory location to be programmed. 3. pd is data to be programmed at byte address. 4. d 7 is the output of the complement of the data written to the device. 5. d out is the output of the data written to the device. figure 19. ac waveforms for byte write operations d out pd t ah data polling t df t oh t oe t ds t cs t wph t dh t wp t ghwl addresses ce oe we data d 7 aaaah pa a0h pa t wc t rc t as t whwh3 t ce 5/4/98 amc0xxcflka 37 ac characteristicsalternate ce controlled writes write/erase/program operations notes: 1. rise/fall e10 ns. 2. maximum specification not needed due to the internal stop timer that will stop any erase or write operation that exceed the device specification. 3. card enable controlled programming: flash programming is controlled by the valid combination of the card enable (ce 1, ce 2) and write enable (we ) signals. for systems that use the card enable signal(s) to define the write pulse width, all setup, hold, and inactive write enable timing should be measured relative to the card enable signal(s). 4. embedded program operation of 16 m s consist of 10 m s program pulse and 6 m s write recovery before read. this is the min- imum time for one pass through the programming algorithm. d5 = 1 only after a byte takes longer than 48 ms to write. card speed parameter symbol parameter description -150 ns unit jedec standard min max t avav t wc write cycle time 150 ns t avel t as address setup time 20 ns t elax t ah address hold time 55 ns t dveh t ds data setup time 50 ns t ehdx t dh data hold time 20 ns t gldv t oe output enable hold time for embedded algorithm 20 ns t ghel read recovery time before write 0 m s t wlel t ws we setup time before ce 0ns t ehwh t wh we hold time 0 ns t eleh t cp ce pulse width 65 ns t ehel t cph ce pulse width high (note 3) 50 ns t eheh3 embedded programming operation (notes 3, 4) 16 m s 48 ms t eheh4 embedded erase operation for each 64k byte memory sector (notes 1, 2) 1.5 s t vcs v cc setup time to write enable low 50 ms 38 amc0xxcflka 5/4/98 switching waveforms 18723c-21 notes: 1. figure indicates last two bus cycles of four bus cycle sequence. 2. pa is address of the memory location to be programmed. 3. pd is data to be programmed at byte address. 4. d 7 is the output of the complement of the data written to the device. 5. d out is the output of the data written to the device. figure 20. alternate ce controlled byte write operation timings d out pd t ah data polling t ds t ws t cph t dh t cp t ghel addresses we oe ce data v cc d7 aaaah pa a0h pa t wc t as t whwh3 or 4 t wh t vcs 5/4/98 amc0xxcflka 39 card information structure the c series card contains a separate 512 byte eeprom memory for the card information structure (cis). all or part of the 512 byte could be used for the cards attribute memory space. this allows all of the flash memory to be used for the common memory space. part of the common memory space could also be used to store the cis if more than 512 bytes of cis are needed. the eeprom used in the c series card is a nec m pd28c05gx-20-eja designed to operate from a 5 v single power supply. the m pd28c05 provides a data polling function that provides the end of write cycle and auto erase and programming functions. table 10 shows the cis information stored in the amd flash memory card. system design and interface information power up and power down protection amds flash memory devices are designed to protect against accidental programming or erasure caused by spurious system signals that might exist during power transitions. the amd pc card will power-up into a read mode when v cc is greater than v lko of 3.2 v. erasing of memory sectors or memory segments can be accomplished only by writing the proper erase com- mand to the card along with the proper chip enable, output enable and write enable control signals. hot in- sertion of pc cards is not permitted by the pcmcia standard. note: hot insertion is defined as the socket condition where the card is inserted or removed with any or all of the following conditions present: v cc = v cch , v pp =v pph , address and/or data lines are active). system power supply decoupling the amd flash memory card has a 0.1 m f decoupling capacitor between the v cc and the gnd pins. it is rec- ommended the system side also have a 4.7 m f capac- itor between the v cc and the gnd pins. 40 amc0xxcflka 5/4/98 table 10. amds cis for c series card tuple address 2 mbyte card tuple value tuples and remarks 00h 01h cistpl_device [common memory] 02h 03h tpl_link 04h 53h flash device, card speed: 53h = 150 ns 06h 0dh/06h/fch/9dh card size: 0dh = 1 mb, 06h = 2 mb, fch = 4 mb, 9dh = 10 mb 08h ffh end of tuple 0ah 18h cistpl_jedec [common memory] 0ch 02h tpl_link 0eh 01h amd mfg id code 10h a4h device id code: a4h = 4 mbit device 12h 1eh cistpl_devicegeo 14h 06h tpl_link no ffh terminator 16h 02h dgtpl_bus: bus width 18h 11h dgtpl_ebs: 11h = 64k byte erase block size 1ah 01h dgtpl_rbs: read byte size 1ch 01h dgtpl_wbs: write byte size 1eh 01h dgtpl_part: number of partition 20h 01h fl device interleave: no interleave 22h 15h cistpl_vers1 24h 03h tpl_link 26h 04h major version number 1 28h 01h minor version for pcmcia std. 2.0 2ah ffh end of tuple 2ch 17h cistpl_device_a [attribute memory] 2eh 04h tpl_link 30h 47h eeprom with extended speed 32h 3ah extended speed = 250 ns 34h 00h device size = 1 unit of 512 byte 36h ffh end of tuple 38h 80h vendor-specific tuple 3ah 0ah tpl_link 3ch 41h a 3eh 4dh m 40h 44h d 42h 26h & 44h 42h b 46h 45h e 48h 52h r 4ah 47h g 4ch 00h end text 4eh ffh end of tuple 50h 81h vendor specific tuples: 81h : xxh ascii characters : xxh : 6ah xxh ascii characters 6ch ffh cistpl_end 5/4/98 amc0xxcflka 41 physical dimensions* type 1 pc card trademarks copyright ? 1996 advanced micro devices, inc. all rights reserved. amd and the amd logo are registered trademarks of advanced micro devices, inc. embedded erase and embedded program are trademarks of advanced micro devices, inc. product names used in this publication are for identification purposes only and may be trademarks of their respective companies . 10.0 min (mm) 10.0 min (mm) 85.6 0.2 mm 54.0 0.1 mm 3.3 0.1 mm 34 1 35 68 front side back side 42 amc0xxcflka 5/4/98 data sheet summary for amc0xxcflka pin description added description for reg pin. table 3. even byte command definitions each density card now has a list of paired segment numbers. the address increment for even bytes should be (n/2) * 100000h. added note 5 for clarification. note 3 requires use of ce 1, not ce 2, and a21. note 2 was clarified. table 4. odd byte command definitions each density card now has a list of paired segment numbers. the address increment for even bytes should be (n-1/2) * 100000h + 80000h. added note 5 for clarification. note 3 requires use of ce 2, not ce 1, and a21. note 2 was clarified. autoselect operation data is a4h. table 5. word command definitions added note 7 for clarification. note 3 requires use of ce 1 and ce 2 and a21. note 5 was modified to reflect that the address should be (addr) + m * (100000h). note 2 was clarified. autoselect operation data is 0101/a4a4h. sector erase clarified that any sector number can be loaded into the sector erase buffer. toggle bitd6 added clarification that d6 is used for entering sector erase suspend mode. sector erase suspend repeated sentence was deleted. write operation status table d3 in exceeded time limit mode is 0. figure 5. ac waveforms for data polling during embedded algorithm operations corrected t whwh3 or 4 . removed erroneous t oe reference. figure 6. ac waveforms for toggle bit during embedded algorithm operations clarified diagram. embedded algorithm flow charts figures 6, 7, 11 references to 14 m s time outs were cor- rected to 16 m s. dc characteristicsbyte-wide operation note 1 has been modified to show standby current is in- creased by: 19 ma for 10 mb, 7 ma for 4 mb, 3 ma for 2mb and 1 ma for 1 mb card in ttl modes. dc characteristicsword-wide operation for ce , reg , we , oe , i il minimum is C300 m a. note 1 has been modified to show standby current is in- creased by: 18 ma for 10 mb, 6 ma for 4 mb, and 2 ma for 2 mb card in ttl modes. ac characteristicswrite/erase/program operations t whwh4 applies to 64k byte sectors. note 1 was modi- fied to exclude the statement regarding preprogram- ming time. figure 19. ac waveforms for byte write operations t whwh1 is now t whwh3 . the unlock address was changed to aaaah according to the byte write se- quence. added t. ac characteristicsalternate ce controlled writeswrite/erase/program operations t whwh4 applies to 64k byte sectors. note 1 was modi- fied to exclude the statement regarding preprogram- ming time. figure 20. alternate ce controlled byte write operation timings added t vcs and t eheh3 or 4 to figure 18. table 10. amds cis for amc0xxcflka removed bracketed reference for tuple address 04h. tuple address 32h now reflects cis memory speed of 250 ns (3ah). revision b+1 sector erase suspend removed the statement requiring the address of a sec- tor not being erased for valid d6 status. trademarks copyright ? 1998 advanced micro devices, inc. all rights reserved. amd, the amd logo, and combinations thereof are registered trademarks of advanced micro devices, inc. product names used in this publication are for identification purposes only and may be trademarks of their respective companies . |
Price & Availability of AMC001CFLKA
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |